Lab1.-Digital-design-and-verification-practice.md

@@ -36,13 +36,108 @@
 
 - Incremental
 
+## git commands
+
+- git clone
+- git add
+- git pull
+- git commit
+- git push
+- git merge
+
+## git reference
+
+[https://www.git-scm.com/doc](https://www.git-scm.com/doc)
+
 
 # HOW TO USE IVERILOG
 
+## STEP 1: Add system call to dump waveform in your verilog source
+
+```verilog
+initial begin
+    $dumpfile(“wave_file.vcd”);
+    $dumpvars(0, testbench_name);
+end
+
+```
+
+## STEP 2: Compilation and Elaboration(generate runtime)
+
+```shell
+iverilog –o runtime_file source.v
+```
+
+## STEP 3: Generating waveforms from runtime
+
+```shell
+vvp –n runtime_file –lxt2
+```
+## iverilog reference
+
+iverilog homepage: [https://steveicarus.github.io/iverilog/](https://steveicarus.github.io/iverilog/)
+
+For windows platform: [http://bleyer.org/icarus/](http://bleyer.org/icarus/)
+
+
 # HOW TO USE GTKWAVE
 
+## Usage
+
+```shell
+gtkwave your_waveform_file.vcd
+```
+
+## gtkwave reference
+
+[https://steveicarus.github.io/iverilog/usage/gtkwave.html](https://steveicarus.github.io/iverilog/usage/gtkwave.html)
+
 # SIPEED TANG PRIMER 20K
 
+## Core module
+
+![image](uploads/34774a75da90f108f858d5fda8c6238f/image.png)
+
+## Core Specifications
+
+- Based on GW2A-LV18PG256C8/I7
+- 20736 x LUT4
+- 15552 x FF
+- Distributed SRAM 41472bit
+- Block SRAM 828Kbit in 46 blocks
+- 48 x Multipliers(18x18)
+- 4 x PLLs
+- 8 x I/O banks
+
+## Dock
+
+![image](uploads/cbb4382a23dbaba80a214df170335dea/image.png)
+
+## Dock specifications
+
+- 40P RGB565 I/F(Interface)
+- 24P DVP I/F
+- 10P Microphone I/F
+- 4 x PMOD
+- 2 x USB Type-C(1 custom USB, 1 USB-JTAG+UART)
+- 48 x Multipliers(18x18)
+- 6 x Keys
+- 6 x LEDs
+- HDMI
+- Ethernet
+- RGB LED(WS2812)
+
+## Tang Primer 20K Schematics
+
+Webpage: [https://dl.sipeed.com/shareURL/TANG/Primer_20K/02_Schematic](https://dl.sipeed.com/shareURL/TANG/Primer_20K/02_Schematic)
+
+Dock schematic: [https://dl.sipeed.com/fileList/TANG/Primer_20K/02_Schematic/Tang_Primer_20K_Dock-3713_Schematics.pdf](https://dl.sipeed.com/fileList/TANG/Primer_20K/02_Schematic/Tang_Primer_20K_Dock-3713_Schematics.pdf)
+
+Core Module schematic: [https://dl.sipeed.com/fileList/TANG/Primer_20K/02_Schematic/Tang_Primer_20K_SOM-3961_Schematic.pdf](https://dl.sipeed.com/fileList/TANG/Primer_20K/02_Schematic/Tang_Primer_20K_SOM-3961_Schematic.pdf)
+
+Documents for Tang Primer 20K: [https://wiki.sipeed.com/hardware/en/tang/tang-primer-20k/primer-20k.html](https://wiki.sipeed.com/hardware/en/tang/tang-primer-20k/primer-20k.html)
+
+
 # FPGA DEVELOPMENT FLOW
 
 # TASK1