| ... | ... | @@ -182,8 +182,142 @@ gtkwave wave.vcd & |
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## STEP5 (optional):pre-synthesize simulation
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Add FPGA macro cell/primitive models to verify if it will work fine with FPGA implementation.
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# TASK1
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find `prim_sim.v` at `/where_your_gowin_installed/gowin_ide/IDE/simlib/gw2a/`
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It should look like this:
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## STEP6: Create a FPGA project, add PIN/Timing constraints, and synthesize design
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Refer to:
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[https://wiki.sipeed.com/hardware/en/tang/tang-primer-20k/primer-20k.html](https://wiki.sipeed.com/hardware/en/tang/tang-primer-20k/primer-20k.html)
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When select device, choose "GW2A-LV18PG256C8/I7"
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## STEP6: Create a FPGA project, add PIN/Timing constraints, and synthesize design
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When adding source files, choose **NOT** to copy files into source directory.
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Add new physical constraints file into project to define PINs
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Edit “.cst” file to add PINs map info
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```
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//Refer to Sipeed Tang Primer 20K
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//define location of signals
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IO_LOC “clk_in” H11;
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IO_LOC “rst_n” C7; //Key_5 on Primer 20K
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//define I/O level property
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IO_PORT “clk_in” IO_TYPE=LVCMOS33;
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IO_PORT “rst _n” IO_TYPE=LVCMOS33;
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//define I/O pull-up/down property
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IO_PORT “clk_in” PULL_MODE=UP;
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IO_PORT “rst _n” PULL_MODE=UP;
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```
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If you have a multiple module project, you need to designate “TOP MODULE” in Hierarchy tab before synthesize
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## STEP7(optional): Post synthesize simulation
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Right click “Place & Route”, select “Configuration”, modify “Generate Post-PnR Verilog Simulation Model file” to “True” to ask GW_IDE to generate post PnR model
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## STEP7(optional): Post synthesize simulation
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After finished PnR, the post-synthesize model called “*.vo” should be found under
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“/prj/your_project_name/impl/pnr” folder
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The file should look like this
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Substitute your original module file with this file in “run_sim.sh” . There is no need to copy, just modify the file path in script
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## STEP8: Place and Route
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## STEP9: Download bitstream
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### 1. Connect board with USB type-C data cable.
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### 2. If you have installed openFPGALoader, try detecting board with:
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```shell
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openFPGALoader --detect
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```
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The result should look like this:
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### 3. Enter the folder where *.fs file is, run following command
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```shell
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openFPGALoader –b tangprimer20k your_design.fs
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```
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**NOTE: as design always changes, there is no need to download into FLASH, DO NOT add “-f” param.**
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## STEP10: Function validation
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---
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# TASK1:
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**Using Sipeed Tang Primer 20K to implement running LEDs.**
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## TIPS:
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- Find LED pins from dock schematics
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- Using FPGA internal OSC
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refer to: [https://www.gowinsemi.com/upload/database_doc/1844/document/65c0a2ec8d029.pdf](https://www.gowinsemi.com/upload/database_doc/1844/document/65c0a2ec8d029.pdf)
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before simulating, copy prim_sim.v from “/where_your_gowin_installed/gowin_ide/IDE/simlib/gw2a/” folder to your “/sim” folder.
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**NOTE that we need a very low frequency clock, design a clock divider to generate 1Hz clock**
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- Sipeed examples for light an LED
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[https://wiki.sipeed.com/hardware/en/tang/tang-nano-20k/example/led.html](https://wiki.sipeed.com/hardware/en/tang/tang-nano-20k/example/led.html)
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# TASK2
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**Connect 4-digit LED segment display to Sipeed Tang Primer 20K board to implement a counter increasing every 1 second.**
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## TIPS:
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### 1. Add a 220 Ohm resistor in serial between LED segment display and FPGA pins, to limit current through LEDs.
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### 2. How to identify PINs
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### 3. As the “digit select” signal (CC pins on LED segment display) should switch around at about 100Hz, an additional 400Hz clock signal should be given by system.
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# TASK2 |
