Lab1.-Digital-design-and-verification-practice.md

+# GENERIC FLOW
+
+## Generic work flow for FPGA
+
+![image](uploads/6ac998b1ce04b17eb84ebc0c6ae0b6c4/image.png)
+
+## Generic work flow for ASIC
+
+![image](uploads/615686cfc0e7b5eb0d83411901ab3c7d/image.png)
+
+## Generic work flow with tools
+
+![image](uploads/449d0a19b3f66e1d4e5964d898ecd717/image.png)
+
+## Using "git" for version control
+
+- Version control for code and docs
+-- Easy to merge
+-- Easy to reverse change
+-- Easy to branch
+-- Easy to track issues
+
+- Collaborate development
+-- Code/docs can be modified by more person
+-- Parallel development
+
+- Text based
+
+- Distributed database
+
+- Incremental
+
+
+# HOW TO USE IVERILOG
+
+# HOW TO USE GTKWAVE
+
+# SIPEED TANG PRIMER 20K
+
+# FPGA DEVELOPMENT FLOW
+
+# TASK1
+
+# TASK2