Lab1.-Digital-design-and-verification-practice.md

@@ -140,6 +140,50 @@ Documents for Tang Primer 20K: [https://wiki.sipeed.com/hardware/en/tang/tang-pr
 
 # FPGA DEVELOPMENT FLOW
 
+## STEP1: download sample project/template with ‘git’
+
+```shell
+git clone https://git.tongji.edu.cn/intelli_chip_and_system_design_course/system_design/fpga_dev_sample.git
+```
+After download, the directory should look like this:
+
+![image](uploads/40c4cccae33fdcd09f656684e44d44fc/image.png)
+
+## STEP2: Editing testbench file as the top level of the system
+
+## STEP3: Editing your modules
+
+## STEP4: Do some simulation to verify if your module works as you expect
+
+enter the /sim folder where tb_top.v is
+
+```shell
+cd sim
+```
+add execution property to “run_sim.sh”
+
+```shell
+chmod +x run_sim.sh
+```
+execute this shell script
+
+```shell
+./run_sim.sh
+```
+
+Content of "run_sim.sh" should look like this:
+
+```shell
+#!/bin/bash
+iverilog -o simrun ./tb_top.v ../rtl/my_design.v
+vvp -n simrun -lxt2
+gtkwave wave.vcd &
+```
+
+![image](uploads/fd8d1d16546e1aa235390032451299e8/image.png)
+
+
+
 # TASK1
 
 # TASK2