2e-find-infomation-for-System-Verilog.md

+Search for information on your own, understand the differences between System Verilog (SV) and Verilog, and try writing a Testbench using System Verilog that can produce the following excitation waveforms. Note that writing operation on BUS A or B should be encapsulated into SV functions.
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+![图片](uploads/939e0b74a6b8faa11456fbae0874dcfe/图片.png)
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